This dissertation presents a 12-bit 1.1 GS/s single-channel pipelined-SAR ADC implemented in a 28nm CMOS technology. A new technique that provides adaptive inter-stage redundancy is proposed to mitigate the speed overhead of the conventional inter-stage redundancy bit. In addition, the first-stage CDAC is implemented with a large-DAC and a small-DAC to improve the settling speed during the bit conversions, and a high-speed detect-and-skip decoder with minimum power overhead is incorporated to reduce the switching power without affecting the high-speed operation. The adaptive inter-stage redundancy improves the speed of the third stage by 10%. The CDAC1 improves the speed of the first stage by 11% and reduces the switching power on large-DAC by 25%. Overall, the single-channel ADC achieves an SNDR of 60.1 dB and an SFDR of 75.3 dB at Nyquist input operating at 1.1 GS/s. With 8.5mW power consumption at a 0.9 V power supply, it achieves a Walden FOM of 9.3$fJ/conv.-step$ and a Schreier FOM of 168.2 dB.

Degree Date

Spring 2024

Document Type


Degree Name



Electrical and Computer Engineering


Ping Gui



Creative Commons License

Creative Commons Attribution-Noncommercial 4.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial 4.0 License

Available for download on Sunday, May 02, 2027