Micah Thornton, Daphne Hwong, Yi Sun, Allison Garcia, Soha Alhelaly, Geoff Shofner, LeRoy Winemberg
Structural tests have many advantages over functional patterns. The fault coverage of structural patterns is generally higher and easier to quantify, well-known algorithms are available to generate them, and they are often a much easier choice for debugging and diagnosis. However, depending on the fault models used, traditional structural patterns can still miss many defects, such as the defects that may occur inside the standard cells, and when chips are placed on a board, they may fail in functional mode even if they pass all structural tests. This can happen even if those same structural tests are applied in-system on the board, making debug very difficult.
Cell-aware faults have been proposed to model those defects inside the standard cells and allow ATPG tools to target them. In some cases, for small circuits, the test set is reasonably short. However, for industrial circuits, the test sets that obtain 100% cell-aware fault coverage are often much too long to be applied efficiently. One previous study has shown that the increase in test pattern count may be more than 50% to 80%. The goal of this research is to reduce the time required to apply test sets capable of detecting cell-aware faults. In this dissertation, we explore an approach that involves the insertion of Design for Testability (DFT) logic into the circuit to utilize the wasted scan- shift clock cycles to enhance the fortuitous detections of cell-aware faults. In particular, we consider an approach that allows data to be captured in shadow flip-flops during scan shift, where those flip-flops have been collected into a MISR (Multiple Input Signature Register) to allow a single signature to be obtained.
In this investigation, we initially fault simulated all scan-shift clock cycles for a given stuck-at fault test set to determine which flip-flops should be shadowed and included in the MISR. Unfortunately, fault simulating this many patterns is very time consuming and may be impractical for large circuits—especially if the scan chains are also long. This fault simulation is also needed to identify which cell-aware faults may still be missed by the intermediate shift patterns so that additional top-off patterns may be added. Finally, the area overhead required to maximize cell-aware fault detection using shadow flops may be prohibitive for some circuits. To resolve these issues, we considered several optimizations. First, we use scan shift cycle sampling to reduce the fault simulation time, and we designed a MISR capture controller to allow scan shift capture to happen at regular intervals. Second, we use fault cones to predict which flip-flops should be shadowed without doing any fault simulation. Finally, we explored algorithms for selecting shadow flops to best trade off additional fault coverage with additional area overhead and further reduced test set size by using a heuristic that iteratively ran ATPG multiple times with varying fault lists.
Computer Science and Engineering
Design for Testability
Number of Pages
Creative Commons License
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Zhang, Fanchen and Dworak, Jennifer, "Cell-Aware Fault Analysis and Test Set Optimization in Digital Integrated Circuits" (2018). Computer Science and Engineering Theses and Dissertations. 4.