Subject Area

Computer Science


Modern System-on-Chips (SoCs) provide benefits such as reduction in overall system cost, and size, increased performance, and lower power consumption. Increasing complexity of these Integrated Circuits (ICs) has resulted in a higher probability of manufacturing defects. Manufacturing defects can result in the faulty operation of a system. Thus, it is essential to test an IC after it is manufactured to detect any possible faults in it. These SoCs include on-chip embedded instruments that can be used for test, debug, diagnosis, validation, monitoring, characterization, configuration, or functional purposes. IEEE 1687 Std. (IJTAG) provides a standard interface for the reconfigurable access and control of on-chip embedded instruments. Fast, and accurate tests are very desirable to the IC manufacturers to reduce time to market for their products.

To overcome some of the challenges associated with modern SoC testing, we designed novel IJTAG based designs that improve the overall bandwidth, and security of the test network. Bandwidth improvements were done using our new broadcast network design, and Parallel-IJTAG network design. We evaluated previously proposed secure IJTAG designs for their susceptibility to side-channel attacks, and explored mitigation strategies. Applying test data in parallel to different SoC partitions may result in higher peak power consumption during test compared to the functional power specifications, thus causing test slowdowns and/or producing erroneous test results. We devised a new graph coloring algorithm which helps in designing systems that require lower peak power consumption during SoC testing.

Degree Date

Spring 5-19-2018

Document Type


Degree Name



Computer Science and Engineering


Jennifer Dworak

Number of Pages




Creative Commons License

Creative Commons Attribution-Noncommercial 4.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial 4.0 License