Optical communication standards from 100 Gb/s to 200 Gb/s to 400 Gb/s generate the growing demands on the performance of ADC than ever before. For example, the 400 Gb/s interconnect framework requires 28 GHz, 37 GHz, 56 GHz and 112 GHz bandwidth ADC for 256-QAM, 64-QAM, 16-QAM and QPSK modulation, respectively. This thesis presents a 56 GS/s 8 bit ADC in 28 nm CMOS. A low-noise parametric amplifier constituted by T/H circuit and sub-channel buffer is proposed to amplify the signal for the improvement of SNR and maintain the good linearity. A switched sub-channel buffer is also proposed that can be turned on during the track phase, thus avoiding the settling errors and achieving better linearity. To enhance the bandwidth, the ESD protection circuit is moved to the common-mode node instead of the input signal nodes to reduce the input parasitic capacitance; The input buffers are utilized to drive the heavy load presented by the T/H circuits; The inductive peaking is exploited at the inputs to tune out some parasitic capacitance; The parasitic capacitors of T/H circuits are used as sampling capacitors instead of adding extra sampling capacitor. The measurement results show that input bandwidth of the ADC is 31.5 GHz and the ENOB is 5.2 bit up to Nyquist frequency, fulfilling the ADC requirements of 224 Gb/s DP-16QAM coherent receivers.
Electrical and Computer Engineering
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Sun, Kexu, "A 56-GS/s 8-Bit Time-Interleaved SAR ADC in 28-nm CMOS" (2018). Electrical Engineering Theses and Dissertations. 12.