This research mainly focuses on the design of a novel memory I/O interface with high bandwidth and high energy-efficient for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed memory I/O interface, exploiting multi-modulation and multi-band signaling, is capable of supporting simultaneous bidirectional data transition of 4 separate data streams across a single-ended off-chip transmission line to achieve both high speed data rate and low power consumption. This multi-band multi-modulation interface (MMI) consists of multiple RF-band transceivers which utilize ASK modulation, and baseband transceivers which utilize 4-PAM modulation to increase the I/O bandwidth while supporting simultaneous bidirectional communication. The MMI circuit was implemented in 65nm CMOS process technology. Testing results show that the MMI interface achieves an overall data rate of 14Gb/s/pin and a better energy efficiency of 2.8pJ/b/pin compared to prior works.
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YU, YUE, "A Low Power High Speed Mobile Memory I/O Interface Using Reconfigurable Multi-Band Multi-Modulation Signaling" (2017). Electrical Engineering Theses and Dissertations. 2.
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