Abstract
High-performance integrated Analog-to-Digital Converters (ADC) play an indispensable role in digital processing since they are the interface circuits that bridge the analog world and digital regime. Successive Approximation Register (SAR) ADCs have been gaining more interests in recent years due to their power efficiency and digital friendliness. However, the conversion speed of SAR ADCs is less competitive than other ADC architectures because of its binary search mechanism. This study presents a 400MS/s 8-bit SAR ADC using multiple concurrent comparators to enhance the conversion speed. Additionally, CMOS T/H circuit and dummy switch are also implemented to increase linearity and compensate charge injection. SAR logic is improved in addition to increase the conversion speed further. Simulation results have shown the effectiveness of the proposed SAR ADC. The proposed design is designed in 65nm CMOS technology and achieves an SNDR of 44dB at 400MS/s for a Nyquist input while consuming 530μW.
Degree Date
Winter 2019
Document Type
Thesis
Degree Name
M.S.E.E.
Department
Electrical and Computer Engineering
Format
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial 4.0 License
Recommended Citation
Fu, Tao, "High-Speed Successive Approximation Register (SAR) ADC Design with Multiple Concurrent Comparators" (2019). Electrical Engineering Theses and Dissertations. 28.
https://scholar.smu.edu/engineering_electrical_etds/28
