Serial transceiver links are widely used for high-speed point-to-point communications. This dissertation describes two transceiver link designs for two different applications.
In serial wireline communications, security is an increasingly important factor to concern. Securing an information processing system at the application and system software layers is regarded as a necessary but incomplete defense against the cyber security threats. In this dissertation, an asynchronous serial transceiver that is capable of transmitting and receiving an auxiliary data stream concurrently with the primary data stream is described. The transceiver instantiates the auxiliary data stream by modulating the phase of the primary data without affecting the primary channel transmission and recovery mechanisms. Standard receiver interoperability is maintained since the auxiliary data appears as primary data jitter. The proposed transceiver with the auxiliary channel can be widely used in many data communication applications such as for transmitting signatures for authentication or other control information, steganography, or additional data in an existing serial link.
The Deep Underground Neutrino Experiment (DUNE) requires that the front-end transmitters operate at cryogenic temperature and drive 25-35 meters long twin-axial (twinax) cables. To compensate the frequency-dependent channel loss over the long cables and alleviate the de-emphasizing of the low-frequency signal magnitude, a hybrid of a current-mode (CM) transmitter equalization (TXEQ) and a voltage-mode (VM) pre-emphasis is proposed. The TXEQ employs a finite-impulse response (FIR) filter to boost the high-frequency components while de-emphasizing the low-frequency signal magnitude, thereby flattening the overall channel frequency response and reducing the Intersymbol Interference (ISI). The VM pre-emphasis is proposed to further mitigate ISI by boosting the high-frequency portion without degrading the signal magnitude, allowing for high signal swing. The main driver utilizes VM source-series-terminated (SST) output stages, which offers higher signal swing and better power efficiency than the conventional current-mode logic (CML) drivers. To ensure the lifetime and reliability at cryogenic temperature, the transmitter is implemented in a 65-nm CMOS process operating at 1.1 V of supply voltage and employing transistors with larger than minimum lengths. Silicon measurement results have validated the proposed approaches.
Electrical and Computer Engineering
Communication, Computer Engineering
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Wang, Xiaoran, "A 2.56 Gbps Serial Wireline Transceiver that Supports An Auxiliary Channel and A Hybrid Line Driver to Compensate Large Channel Loss" (2020). Electrical Engineering Theses and Dissertations. 37.