Jennifer Dworak, Theodore Manikas, Kundan Nepal
More stringent defect detection requirements have led to the creation of new fault models, such as the cell-aware fault model, that attempts to model defects that might be missed by traditional test sets. Unfortunately, the resulting test sets can be long, and thus we have previously explored a DFT-based (Design for Testability-based) approach to reduce test time by harnessing scan shift cycles for cell-aware defect detection. This approach uses a MISR (Multiple Input Signature Register) structure to capture data on the functional inputs to selected scan flip-flops during the shifting procedure. The final signature in the MISR can then be compared to an expected signature.
While this DFT structure was shown to be very effective for detecting static cell-aware faults, other faults that are not explicitly modeled as cell-aware faults are also possible. The n-detect test approach was previously proposed to detect faults fortuitously by increasing the number of times that simpler faults (e.g. stuck-at faults) are detected. In this dissertation, we investigate the ability of our DFT MISR circuitry to provide multiple fault detections of the “hardest to detect” stuck-at faults during scan shift. We will show that significant additional stuck-at fault detections are possible in the circuits studied, even when only a subset of all scan chain flops are used for scan shift capture. We explore which flip-flops should be shadowed to increase the value of n for the least detected stuck-at faults, and we then identify which circuit characteristics are most important for determining the cost of the MISR needed to achieve high values of n. For example, circuits that contain a few flip-flops with upstream fault cones that cover a large percentage of all faults in the circuit can often achieve high n-detect coverage fortuitously with a low-cost MISR. This allows a DFT engineer to predict the viability of this MISR-based approach early in the design cycle.
On the other hand, modern integrated circuits (ICs) must be tested for both static and delay defects. As a result, transition fault testing is an important component of modern testing for delay defects. Thus, to detect transition faults, we propose another DFT scan chain structure. Specifically, a Capture Control signal and a Shift Control signal allow the circuit to capture data within the original scan chain while still recovering the original shift pattern and the original captured results at the end of shifting. This dissertation will show that a significant number of transition faults can be detected during scan shift when a stuck-at ATPG pattern set is applied and sometimes shifted at-speed in a ``Launch-on-Shift'' (LoS) mode of operation. Furthermore, with selected top-off LoS patterns generated by a commercial tool, higher transition fault coverages are obtained than even with the commercial tool's original launch-on shift transition fault pattern set.
Electrical and Computer Engineering
Number of Pages
Jiang, Hui, "Enhanced Design for Testability Circuitry for Test" (2022). Electrical Engineering Theses and Dissertations. 45.