Abstract
A 1-GS/s 8-bit single-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) using coarse and fine comparators with fully background comparator offset calibration is presented. Low-power coarse comparators and low-noise fine comparators are both employed to improve the comparator power efficiency. Non-binary digital-to-analog converter (DAC) with redundancy is employed to tolerate possible errors in the most-significant-bit (MSB) decisions. A novel comparator offset calibration scheme is proposed to remove the offsets between the different comparators, without slowing down the speed of the SAR conversion. The prototype ADC is simulated in a 28 nm CMOS technology and achieves an SNDR of 42.13 dB near Nyquist frequency while consuming 3.2 mW.
Degree Date
Spring 5-19-2018
Document Type
Dissertation
Degree Name
Ph.D.
Department
Electrical and Computer Engineering
Advisor
Ping Gui
Number of Pages
105
Format
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial 4.0 License
Recommended Citation
Wang, Guanhua, "High-Speed Single-Channel SAR ADC Using Coarse and Fine Comparators with Background Comparator Offset Calibration" (2018). Electrical Engineering Theses and Dissertations. 9.
https://scholar.smu.edu/engineering_electrical_etds/9
Included in
Electrical and Electronics Commons, VLSI and Circuits, Embedded and Hardware Systems Commons
