A 1-GS/s 8-bit single-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) using coarse and fine comparators with fully background comparator offset calibration is presented. Low-power coarse comparators and low-noise fine comparators are both employed to improve the comparator power efficiency. Non-binary digital-to-analog converter (DAC) with redundancy is employed to tolerate possible errors in the most-significant-bit (MSB) decisions. A novel comparator offset calibration scheme is proposed to remove the offsets between the different comparators, without slowing down the speed of the SAR conversion. The prototype ADC is simulated in a 28 nm CMOS technology and achieves an SNDR of 42.13 dB near Nyquist frequency while consuming 3.2 mW.
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Wang, Guanhua, "High-Speed Single-Channel SAR ADC Using Coarse and Fine Comparators with Background Comparator Offset Calibration" (2018). Electrical Engineering Theses and Dissertations. 9.
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