High-performance, low-power, and high-accuracy circuit design with a compact silicon area is necessary for a wide range of current applications. Three-dimensional integrated circuits (3D ICs) can be a promising solution that overcomes the technical barriers in high-performance communication systems by using their capabilities of chip area reduction, improved signal integrity, and reduced routing complexity. In addition to the 3D integration, to achieve the optimum power efficiency, signal quality, and minimum supply noises on a heterogeneous stacking, utilizing computational intelligence methods by considering all design parameters (e. g., TSV and transistor sizing, and placement) can be significantly favorable.
This dissertation presents multiple novel 3D IC designs in digital and mixed-signal systems with their fabricated chip prototypes. An evolutionary approach has also been utilized on the design to further improve the circuit performance. Exploiting the multi-objective evolutionary algorithms on the circuit sub-blocks and TSVs has provided the overall system specification enhancement regarding performance, power efficiency, delay, noise, and silicon area for the proposed 3D architectures.
The implemented novel 3D prototypes include analog to digital converter (ADC), clock distribution network (CDN), power distribution network (PDN), and high speed I/O memory interface. The proposed on-chip 3D architectures are analyzed, designed, and fabricated in 65nm complementary metal–oxide–semiconductor (CMOS) technologies at 1.0 V. The measured results show utilizing both 3D IC integration and evolutionary algorithms have significantly improved several important circuit factors regarding performance, power, jitter, latency, accuracy, chip area, and speed in all the implemented prototypes.
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Mirzaie, Nahid, "PERFORMANCE-AWARE AND POWER-EFFICIENT THREE DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) DESIGN UTILIZING EVOLUTIONARY ALGORITHMS" (2019). Electrical Engineering Theses and Dissertations. 24.