Abstract

This dissertation is comprised of two unrelated design endeavors. The first one is about two CMOS nonreciprocal components: 1) an isolator and 2) a circulator. To make the components compact enough for the next generation communication systems with wide bandwidth, both components operate at 100 GHz band for full-duplex transceivers for ultra-high-data-rate millimeter-wave wireless communication. The proposed nonreciprocal structures are based on a time-domain modulation by signals at around 1/6 of the RF frequencies and spatial duplexing over the RF signal paths, demonstrating over 45 dB isolation in a bandwidth of 1.5 GHz over the tuning range of 85-110 GHz. In the presented isolator, two capacitive mixers together with a biasing network form a resonant type of wideband matching network for lower loss. An enhanced delta topology is proposed for the circulator design which reduces the design complexity and chip area overhead. Implemented in a 65 nm CMOS with a chip area of 0.13 mm2 and 0.21 mm2, respectively, both the isolator and the circulator achieve over 45 dB isolation and better than 10 dB return losses throughout the entire bandwidth. A maximum 4.5 dB and 5.6 dB insertion losses (ILs) are achieved by the isolator and circulator, respectively. The second design endeavor aims at Electromagnetic Interferences (EMI) suppression on DC-DC power converter, especially for the Gallium Nitride (GaN)-based buck converters which operate at high switching frequencies but with high level of EMI noises. A Gaussian switching scheme is realized on chip for the first time for GaN power switches to effectively reduce the EMI level in the high-frequency domain. Meanwhile, spread-spectrum frequency dithering (SSFD) technique is adopted to compress the spurious switching noise in the low-frequency domain. In order to handle high-speed Gaussian switching, a feed-forward segmented driving scheme is proposed to generate precise Gaussian trajectories. The Gaussian slopes are reconfigurable to enable optimization of the power efficiencies for different EMI standards. Implemented in a 180 nm High voltage CMOS process, the presented GaN based buck converter reduces EMI noise by 36.9 dB and 49.1 dB at 10 MHz and 100 MHz respectively. From 250 MHz to 400 MHz and from 400 MHz to 500 MHz, the measured peak EMI noise is reduced by 22 dB and 16 dB, respectively. While the EMI is greatly reduced, the maximum power efficiency is 85.2%, comparable to that of other state-of-the-art GaN gate driving schemes.

Degree Date

Fall 2020

Document Type

Dissertation

Degree Name

Ph.D.

Department

Electrical and Computer Engineering

Advisor

Ping Gui

Number of Pages

101

Format

.pdf

Creative Commons License

Creative Commons Attribution-Noncommercial 4.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial 4.0 License

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