Abstract

The demand for high bandwidth, low latency, reconfigurable, and small form factor memory I/O interface design has significantly increased with the development of data-intensive applications, such as artificial neural networks and high-performance computing. However, the current memory I/O interface technologies have critical limitations, such as limited bandwidth, limited pin count, long latency, non-reconfigurable data access, and large form factor. Therefore, a novel memory I/O interface design is needed to overcome these limitations.

This dissertation presents two novel memory I/O interface designs using 3D integration, QBI, and 8-PAM technologies to improve bandwidth, latency, reconfigurability, and form factor for future mobile devices. The proposed 3D reconfigurable QBI memory I/O interface, which utilizes a baseband (BB) signaling, three RF-band signalings, and a short vertical 3D µbump channel, is capable of reconfigurable data access with low latency and small form factor. Moreover, the pin count is reduced by four times due to four data communication on a shared 3D µbump channel. The proposed 3D 8-PAM memory I/O interface, which utilizes an 8-level signaling and a short vertical 3D µbump channel, enables three data concurrently communication between CPU and memory. As a result, three times higher data rate on the channel, three times less pin, and reconfigurable data access with low latency and small form factor are achieved compared to the conventional memory I/O interface using NRZ. The proposed transceivers' operation and performance are analyzed, and their circuit implementations are discussed in detail. A chip prototype of the 3D QBI transceiver was implemented in a 180 nm CMOS process technology. A two-tier QBI die-stack is implemented to verify the QBI design. Face-to-face configuration with µbump interconnects is used to save cost. The measured results show that the reconfigurable data access with low latency and small form factor is achieved by utilizing both 3D integration and QBI. The proposed 3D 8-PAM transceiver is analyzed, designed, and simulated in a 65nm CMOS technology with a 1.2 V supply. The simulation results show that, by utilizing both 3D integration and 8-PAM, the transceiver exhibits higher aggregate data throughput, better energy efficiency, and lower latency than prior works.

Degree Date

Spring 2021

Document Type

Dissertation

Degree Name

Ph.D.

Department

Electrical and Computer Engineering

Advisor

Duncan L. MacFarlane

Number of Pages

109

Format

.pdf

Creative Commons License

Creative Commons Attribution-Noncommercial 4.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial 4.0 License

Download

Share

COinS