Abstract

Advanced wireless applications require a medium resolution Radio Frequency (RF) sampling Analog to Digital Converter (ADC). By performing sampling of ADC at RF frequency, the mixer and Intermediate Frequency (IF) amplifier can be implemented in the digital domain, which helps the receiver eliminate troublesome mixing spurs and potentially improves the software-defined ratio of the entire system. By combing the merits of the energy-efficient Successive Approximation Register (SAR) ADC and the high-speed pipeline ADC, the SAR-assisted pipeline ADC achieves superior performance in high-speed medium-resolution ADC. However, with the advance of the process, due to the pure analog implementation, the residue amplifier inside the SAR-assisted pipeline ADC acts as a bottleneck in the ADC performance. Thus, it is imperative to explore efficient techniques to improve the performance of the residue amplifier.

This dissertation presents an RF-sampling 1 GS/s 12-bit single-channel SAR assisted pipeline ADC in a 28 nm Complementary-Metal-Oxide-Semiconductor (CMOS) process. A novel Harmonic Injecting Cross-coupled Pair (HXCP) is proposed within a Gm-R-based residue amplifier (RA) design as a critical part of the presented ADC. This technique overcomes the challenges in designing analog circuits using advanced nanometer CMOS processes and achieves the gain and linearity required for the ADC. By implementing the HXCP in a RA, the proposed technique successfully improves the RA linearity by at least 10 dB while boosting the gain of the RA to about 8. The entire ADC consists of three stages, with 4 bits, 4 bits, and 6 bits, respectively. Two 1-bit interstage redundancies are implemented between the three stages. Various techniques help the ADC achieve the targeted speed and resolution. The presented ADC was implemented in a 28nm CMOS process and achieved an Effective Resolution of Bandwidth (ERBW) of 1 GHz, an Signal to Noise and Distortion Ratio (SNDR) of 60.7 dB, an Spurious Free Dynamic Range (SFDR) of 73 dB at Nyquist input (495 MHz), and an SFDR of 82 dB at 1 GHz input. A 7.5 fj/conv-step Walden Figure-of-Merit (FoM) and a 169.4 dB Schrier FoM are achieved, demonstrating one of the best figures of merits among ADCs of similar speed and resolution.

Degree Date

Fall 2021

Document Type

Dissertation

Degree Name

Ph.D.

Department

Electrical and Computer Engineering

Advisor

Ping Gui

Second Advisor

Ronald Rohrer

Third Advisor

Jennifer Dworak

Fourth Advisor

Joseph Camp

Fifth Advisor

Theodore Manikas

Subject Area

Electrical, Electronics Engineering

Number of Pages

90

Format

.pdf

Creative Commons License

Creative Commons Attribution-Noncommercial 4.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial 4.0 License

Available for download on Saturday, December 07, 2024

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