A 2.1 GS/S 2-CHANNEL PIPELINE-SAR ADC WITH SPEED-ENHANCED BOOTSTRAP SWITCH AND LOW-LATENCY SAR LOGIC
Alternative Title
A 2.1 GS/s 2-Channel Pipeline-SAR ADC With Speed-Enhanced Bootstrap Switch and Low-Latency SAR Logic
Contributor
Xianshan wen, Liang Fang, Ping Gui
Abstract
This dissertation introduces a 12-bit 2-channel interleaved Pipelined Successive Approximation Register (Pipelined-SAR) Analog-to-Digital Converter (ADC) capable of operating at 2.1 GS/s. A speedenhanced bootstrap switch that enhances the sampling speed is featured so that the overall speed bottleneck of the 3-stage pipelined SAR structure can be alleviated. In addition, an innovative SAR logic structure, compatible with multiple comparators in a loop-unrolled fashion, is presented. N/P MOS unbalanced sizing technique is implemented in SAR logic to further reduce the propagation delay of both the clocking path and the Capacitive Digital-to-Analog Converter (CDAC) driving path. This work exploits the circuits architectures and design techniques and tradeoffs to achieve multi-Giga sampling frequency without interleaving a large number of channels. Implemented in a 28 nm CMOS process, the ADC achieves an SNDR of 59.1 dB and an SFDR of 76.1 dB at the Nyquist input operating at 2.1 GS/s. With 17.5 mW power consumption at a 0.9 V power supply, it achieves a Walden FOM of 11.4 fj/conv.-step and a Schreier FOM of 166.9 dB.
Degree Date
Fall 2025
Document Type
Dissertation
Degree Name
Ph.D.
Department
Electrical and Computer Engineering
Advisor
Ping Gui
Number of Pages
126
Format
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial 4.0 License
Recommended Citation
Fu, Tao, "A 2.1 GS/S 2-CHANNEL PIPELINE-SAR ADC WITH SPEED-ENHANCED BOOTSTRAP SWITCH AND LOW-LATENCY SAR LOGIC" (2025). Electrical Engineering Theses and Dissertations. 87.
https://scholar.smu.edu/engineering_electrical_etds/87
