Abstract

Silicon photonics allows for the fabrication of many optical elements on a single photonic integrated circuit (PIC). By taking advantage of the established foundry technology used in the CMOS and silicon’s high refractive index, high feature density manufacturing can be achieved in mass quantities. In CMOS fabrication, from conception of an electronic circuit to testing, the process of designing an electronic circuit is dictated by a design flow which has been developed over the course of decades. This flow includes circuit level design and simulation, layout of the circuit, layout and verification of the chip, fabrication, packaging, and testing. Given the identical fabrication technologies used in photonic and electronic circuit manufacturing, electronic design paradigms have been applied to photonic design. Current photonic design puts emphasis on physical layout with minimal simulation. Some post-layout verification exists but is unable to capture complex behavior such as optical and thermal cross-talk between photonic circuits. In addition, there is no design verification besides the traditional design rule check (DRC). To further develop the PIC design process, the need to fully characterize the current state of the photonic design flow is evident. In this work, a design flow is developed for photonic circuits fabricated through the American Institute for Manufacturing Integrated Photonics, or AIM Photonics. More specifically, this design flow has been developed for their Multi-Project Wafer (MPW) Process Design Kits (PDKs). A photonic circuit containing a ring resonator with a heater was designed and simulated using ANSYS Lumerical and laid out in Klayout, an open source layout software for photonic circuits, using the AIM Photonics PDK version 4.5a. This circuit was then characterized in an optics laboratory to compare its physical and simulated performance. Finally, through this comparison, we identified gaps in the current photonic layout and simulation tools as compared to electronic design automation (EDA).

Degree Date

Fall 12-17-2022

Document Type

Thesis

Degree Name

M.S.E.E.

Department

Electrical and Computer Engineering

Advisor

Duncan MacFarlane

Second Advisor

Mitchell Thornton

Third Advisor

Gary Evans

Number of Pages

71

Format

.pdf

Creative Commons License

Creative Commons Attribution-Noncommercial 4.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial 4.0 License

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