Subject Area
Computer Engineering
Abstract
Traditional production screening of digital logic using non–layout-aware port-level fault based scan ATPG patterns, toggle-based activity patterns, and IDDQ-based stress tests has served as an industry standard for several decades to achieve very low outgoing Defective Parts Per Million (DPPM) in integrated circuits. Although these techniques are effective at detecting catastrophic defects that manifest immediately after manufacturing, latent defects must be accelerated through targeted stress mechanisms so that they can be detected prior to product shipment. As FinFET technology nodes continue to scale in the single-digit regime, particularly at 7nm and below, the ability to create, apply, and accurately measure transistor-level stress patterns for complex SoC designs has become increasingly challenging due to heightened layout sensitivity, reduced noise margins, and pronounced process variability. Three-dimensional device architectures (FinFET and Gate-All-Around (GAA), show extreme threshold-voltage variability, and ultra-thin gate dielectrics concentrate electric fields on specific fins or the GAA dielectric that are not captured by simple toggle activity. In addition, aging mechanisms such as 2 time-frame stress-induced Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), tunneling-induced Time-Dependent Dielectric Breakdown (TDDB), and power-grid IR-drop variations require precise combinations of voltage, timing, and duty cycle, where the worst-case stress often occurs when a transistor switches while its drain is held at a high voltage (or vice-versa), a condition toggle coverage patterns v do not enforce. Consequently, toggle-based metrics systematically overestimate stress adequacy and fail to activate the latent high-field conditions responsible for early-life failures at advanced process nodes. This dissertation presents the motivation, necessity, and detailed methodology behind ongoing research into Layout-Aware Defect-Oriented Stress (LA-DOS) scan ATPG pattern generation using User Defined Fault Modeling (UDFM). A comprehensive silicon characterization flow is introduced, encompassing LA-DOS scan ATPG application at the wafer probe across multiple voltage, timing, and temperature corners, followed by stress testing and post-stress validation. The effectiveness of the proposed approach is demonstrated using extensive silicon data collected from five production wafers of an NPI SoC design, enabling cross-wafer and cross-split analysis of stress sensitivity, margin behavior, and pattern-dependent effects. The proposed LA-DOS flow enables the definition and quantification of three new defect-oriented stress coverage KPI that more accurately reflect the true transistor-level and layout-aware resistive defect stress exposure in advanced FinFET technologies. Silicon results highlight significant limitations in traditional toggle coverage metrics, which are shown to systematically overestimate actual stress coverage, particularly in the presence of layout-dependent effects such as Multiple-Input Switching (MIS) and dynamic voltage and timing interactions. Based on these findings, the dissertation concludes with practical recommendations for integrating LA-DOS-based stress ATPG into existing production test flows, providing a scalable path toward sustaining zero-defect automotive-grade quality in single-digit FinFET process nodes.
Degree Date
Spring 5-16-2026
Document Type
Dissertation
Degree Name
Ph.D.
Department
Computer Engineering
Advisor
Dr. Jennifer Dworak
Acknowledgements
The author would like to express his sincere thanks to his advisor Dr. Jennifer Dworak from SMU for her unwavering and strong guidance and mentorship on this research project. The author would also like to extend his sincere appreciation to Yi Sun, Ramanath Dharmavarm & Ravi J N from NXP Semiconductors & Mohammed Zine E. Brahmi, Martina Perkovic & Megan Appel from Dr. Jennifer Dworak’s SMU research team for their significant contributions to the co-development of the LA-DOS UDFM, Stress patterns and 3 new stress Key Product Indicators (KPI): "Transistor Bias Coverage %, Resistive Bridges Coverage % and Resistive Opens Coverage %" flows. The author also gratefully acknowledges Arun Kumar Anjaneyareddy, Sunny (Kiran) Thota, and Archana Ganesh from NXP Semiconductors for their efforts in co-developing and implementing the updated wafer-probe study test-program flow, and for successfully completing the silicon characterization on five virgin N5 Design A wafers using the new LA-DOS stress patterns. The author further extends heartfelt gratitude to his current manager Narasimhan Narayanan (Vice President, ACE Design Methodology & Automation), Brian Sneddon (former Senior Vice President, AES PETE), Srihari Sivaraj (Vice President, AES PETE), Karen Hicks (former Senior Vice President, ACE Corporate Quality), and Dr. Chen He (NXP Fellow, AES PETE) for supporting him in this three-year Long-Term University project, and for placing their trust in him to lead this effort with the SMU research team and drive it to successful completion.
Number of Pages
161
Format
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial 4.0 License
Recommended Citation
Ramesh, Saidapet P., "LA-DOS: Layout-Aware Defect-Oriented Stress SCAN ATPG Pattern Generation & Silicon Wafer(s) Study" (2026). Electrical Engineering Theses and Dissertations. 90.
https://scholar.smu.edu/engineering_electrical_etds/90
Notes
LA-DOS, XTORB, RB, RO, TOGGLE