Subject Area
Electrical, Electronics Engineering
Abstract
This thesis presents an energy-and-area-efficient two-stage comparator implemented in TSMC 65 nm CMOS that incorporates a Floating Inverter Amplifier (FIA) followed by a latch using a common-mode reset scheme. The FIA improves input sensitivity and reduces kickback noise by isolating the input nodes from large latch voltage swings. The proposed latch resets its output nodes to a common-mode voltage rather than one of its supply rails, thereby reducing switching energy during the reset phase. The comparator can resolve differential input voltages as small as 2 mV with a clock period of 500 ps, achieving 74.33 μV input-referred noise while consuming 81.69 fJ per comparison. The proposed design also features a low transistor count in the latch stage, using only 8 transistors.
Degree Date
Spring 5-2026
Document Type
Thesis
Degree Name
M.S.E.E.
Department
Electrical and Computer Engineering
Advisor
Ping Gui
Second Advisor
Theodore Manikas
Third Advisor
Sanjaya Lohani
Number of Pages
61
Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial 4.0 License
Recommended Citation
Yu, Larry, "An Energy- and Area- Efficient Two-Stage Latch Comparator Using Common-Mode Reset" (2026). Electrical Engineering Theses and Dissertations. 89.
https://scholar.smu.edu/engineering_electrical_etds/89
